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Preliminary
Features
* * * * * * * * * *
8-Bit OTP IR Remote Controller
* * * * * * *
HT48RA0A
Operating voltage: 2.2V~3.6V Ten bidirectional I/O lines Six schmitt trigger input lines One carrier output (1/2 or 1/3 duty) On-chip crystal and RC oscillator Watchdog timer 1K14 program EPROM 328 data RAM Low voltage reset function Halt function and wake-up feature reduce power consumption
62 powerful instructions Up to 1ms instruction cycle with 4MHz system clock All instructions in 1 or 2 machine cycles 14-bit table read instructions One-level subroutine nesting Bit manipulation instructions 20-pin SOP package 24-pin SOP package
General Description
The HT48RA0A is an 8-bit high performance RISC-like microcontroller specifically designed for multiple I/O product applications. The device is particularly suitable for use in products such as infrared remote controllers and various subsystem controllers. A halt feature is included to reduce power consumption.
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Preliminary
Block Diagram
STACK P ro g ra m EPROM P ro g ra m C o u n te r S Y S C L K /4 In s tr u c tio n R e g is te r MP M U X DATA M e m o ry F r e q u e n c y D iv id e r W DT L e v e l o r C a r r ie r C a r r ie r C o n tr o l P C 0 C o n tro l
HT48RA0A
P C 0 /R E M
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r
MUX PORT B PB
STATUS
PB0~PB1 PB2~PB7
S h ifte r
PA OSC2 OS RE VD VS
S
PORT A
PA0~PA7
C1 S D
ACC
Pin Assignment
PA1 PA0 PA1 1 2 3 4 5 6 7 8 9 10 PA0 PB1 PB0 P C 0 /R E M VDD OSC2 OSC1 VSS RES 20 19 18 17 16 15 14 13 12 11 PA2 PA3 PA4 PA5 PA6 PA7 PB2 PB3 PB4 PB5 PB1 PB0 P C 0 /R E M VDD OSC2 OSC1 VSS RES NC NC 9 10 11 12 8 7 6 5 4 3 2 1 24 23 22 21 20 19 18 17 16 15 14 13 PA2 PA3 PA4 PA5 PA6 PA7 PB2 PB3 PB4 PB5 PB6 PB7
H T48R A 0A 20 SO P
H T48R A 0A 24 SO P
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Preliminary
Pin Description
Pin Name I/O Code Option Wake-up or none Level or carrier 3/4 Crystal or RC 3/4 3/4 Wake-up or none 3/4 Description
HT48RA0A
PB0, PB1
I/O
2-bit bidirectional input/output lines with pull-high resistors. Each bit can be determined as NMOS output or schmitt trigger input by software instructions. Each bit can also be configured as wake-up input by code option. Level or carrier output pin PC0 can be set as CMOS output pin or carrier output pin by code option. Positive power supply OSC1, OSC2 are connected to an RC network or a crystal (determined by code option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock (NMOS open drain output). Negative power supply, ground Schmitt trigger reset input. Active low. 6-bit schmitt trigger input lines with pull-high resistors. Each bit can be configured as a wake-up input by code option. Bidirectional 8-bit input/output port with pull-high resistors. Each bit can be determined as NMOS output or schmitt trigger input by software instructions.
PC0/REM VDD OSC2 OSC1 VSS RES PB2~PB7 PA0~PA7
O 3/4 I O 3/4 I I I/O
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V Input Voltage .................VSS-0.3V to VDD+0.3V Storage Temperature.................-50C to 125C Operating Temperature ..............-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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Preliminary
D.C. Characteristics
Symbol VDD IDD ISTB VIL1 VIH1 VIL2 VIH2 IOL IOH RPH1 RPH2 VLVR Parameter Operating Voltage Operating Current Standby Current Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) I/O Ports Sink Current PC0/REM Output Source Current Pull-high Resistance of PA Port, PB0~PB1 and RES Pull-high Resistance of PB2~PB7 Low Voltage Reset Test Conditions VDD 3/4 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V Conditions LVR disabled No load fSYS=4MHz No load system HALT 3/4 3/4 3/4 3/4 VOL=0.1VDD VOH=0.9VDD 3/4 3/4 3/4 Min. 2.2 3/4 3/4 0 0.8VDD 0 0.9VDD 1.5 -1 3/4 3/4 2.1 Typ. 3/4 0.7 3/4 3/4 3/4 3/4 3/4 2.5 -1.5 60 60 2.3
HT48RA0A
Ta=25C Max. 3.6 1.5 1 0.2VDD VDD 0.4VDD VDD 3/4 3/4 3/4 3/4 2.5 Unit V mA mA V V V V mA mA kW kW V Ta=25C
A.C. Characteristics
Symbol fSYS tRES tSST Parameter System Clock External Reset Low Pulse Width System Start-up timer Period Test Conditions VDD 3V 3/4 3/4 Conditions 3/4 3/4 Power-up or wake-up from HALT Min. Typ. 400 1 3/4 3/4 3/4 1024
Max. Unit 4000 3/4 3/4 kHz ms tSYS
Note: tSYS=1/fSYS
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Preliminary
Functional Description
Execution flow The HT48RA0A system clock can be derived from a crystal/ceramic resonator oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program counter - PC The 10-bit program counter (PC) controls the sequence in which the instructions stored in program EPROM are executed and its contents specify a maximum of 1024 addresses. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset or return from subroutine, the PC manipulates the program transfer by
T1 S y s te m C lo c k T2 T3 T4 T1 T2
HT48RA0A
loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program memory - EPROM The program memory is used to store the program instructions which are to be executed. It also contains data and table and is organized into 102414 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H
This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H.
T3 T4 T1 T2 T3 T4
In s tr u c tio n C y c le PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution flow
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May 17, 2000
Preliminary
* Table location
000H
HT48RA0A
Any location in the EPROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, the remaining 2 bits are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), where P indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. All table related instructions need 2 cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack register - STACK This is a special part of the memory used to save the contents of the program counter (PC) only. The stack is organized into one level and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack Mode Initial reset Skip Loading PCL Jump, call branch Return from subroutine *9 #9 S9 *8 #8 S8 *9 0 *8 0
D e v ic e in itia liz a tio n p r o g r a m
n00H L o o k - u p ta b le ( 2 5 6 w o r d s ) nFFH
P ro g ra m EROM
3FFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 4 b its N o te : n ra n g e s fro m 0 to 3
Program memory pointer (SP) and is neither readable nor writeable. At a subroutine call the contents of the program counter are pushed onto the stack. At the end of a subroutine signaled by a return instruction (RET), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent return address is stored). Program Counter *7 0 @7 #7 S7 *6 0 @6 #6 S6 *5 0 @5 #5 S5 *4 0 @4 #4 S4 *3 0 @3 #3 S3 *2 0 @2 #2 S2 *1 0 @1 #1 S1 *0 0 @0 #0 S0
PC+2
Program counter Note: *9~*0: Program counter bits #9~#0: Instruction code bits S9~S0: Stack register bits @7~@0: PCL bits
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Preliminary
Data memory - RAM The data memory is designed with 428 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (328). Most of them are read/write, but some are read only. The special function registers include the indirect addressing register (00H), the memory pointer register (MP;01H), the accumulator (ACC;05H) the program counter lower-order byte register (PCL;06H), the table pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the status register (STATUS;0AH) and the I/O registers (PA;12H, PB;14H, PC;16H). The remaining space before the 20H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose data memory, addressed from 20H to 3FH, is used for data and control information under instruction command. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through memory pointer register (MP;01H). Indirect addressing register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses data memory pointed to by MP (01H). Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation. Instruction(s) TABRDC [m] TABRDL [m] *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1D 1E 1F 20 H H G e n e ra l P u rp o s e DATA M EM ORY (3 2 B y te s ) 3FH H H PC PB PA ACC PCL TBLP TBLH STATUS In d ir e c t A d d r e s s in g R e g is te r MP
HT48RA0A
S p e c ia l P u r p o s e DATA M EM ORY
:U nused R e a d a s "0 0 "
RAM mapping
Table Location *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table location Note: *9~*0: Table location bits P9~P8: Current program counter bits @7~@0: Table pointer bits
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Preliminary
The memory pointer register MP (01H) is a 6-bit register. The bit 7~6 of MP is undefined and reading will return the result 1. Any writing operation to MP will only transfer the lower 6-bit data to MP. Accumulator The accumulator closely relates to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. Data movement between two data memory locations has to pass through the accumulator. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions.
* Arithmetic operations (ADD, ADC, SUB,
HT48RA0A
* Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but also changes the contents of the status register. Status register - STATUS This 8-bit status register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PD flags, bits in the status register can be altered by instructions like most other register. Any data written into the status register will not change the TO or PD flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PD flags can only be changed by the Watchdog Timer overflow, chip power-up, clearing the Watchdog Timer and executing the HALT instruction. Function
SBC, DAA)
* Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC)
Labels C
Bits 0
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared when either a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Undefined, read as 0 Undefined, read as 0 Status register
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AC Z OV PD TO 3/4 3/4
1 2 3 4 5 6 7
Preliminary
The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Oscillator configuration There are two oscillator circuits in the HT48RA0A.
OSC1
HT48RA0A
system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift for the oscillator. No other external components are needed. Instead of a crystal, the resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. Watchdog timer - WDT The clock source of the WDT is implemented by instruction clock (system clock divided by 4). The clock source is processed by a frequency divider and a prescaller to yield various time out periods. Clock Source WDT time out period = 2n Where n= 8~11 selected by code option. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by code option. If the Watchdog Timer is disabled, all the exe-
OSC1
OSC2 C r y s ta l O s c illa to r
fS Y S /4 (N M O S o p e n d r a in o u tp u t)
OSC2 RC O s c illa to r
System oscillator Both are designed for system clocks; the RC oscillator and the Crystal oscillator, which are determined by code options. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores the external signal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VSS in needed and the resistance must range from 51kW to 1MW. The
F r e q u e n c y D iv id e r C lo c k S o u r c e ( S y s te m C lo c k /4 ) 3 - b it C o u n te r
C le a r W D T P r e s c a lle r ( 8 - b it)
C o d e O p tio n S e le c t
C ode O p tio n
W DT T im e - o u t
C lo c k S o u r c e 2n
(n = 8 ~ 1 1 )
Watchdog timer
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Preliminary
cutions related to the WDT result in no operation and the WDT will lose its protection purpose. In this situation the logic can only be restarted by an external logic. A WDT overflow under normal operation will initialize chip reset and set the status bit TO. To clear the contents of the WDT prescaler, three methods are adopted; external reset (a low level to RES), software instructions, or a HALT instruction. There are two types of software instructions. One type is the single instruction CLR WDT, the other type comprises two instructions, CLR WDT1 and CLR WDT2. Of these two types of instructions, only one can be active depending on the code option - CLR WDT times selection option. If the CLR WDT is selected (i.e.. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e.. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip due to a time-out. Power down operation - HALT The HALT mode is initialized by the HALT instruction and results in the following...
* The system oscillator turns off and the WDT
HT48RA0A
cuted. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC (Program Counter) and SP, the others keep their original status. The port B wake-up can be considered as a continuation of normal execution. Each bit in port B can be independently selected to wake up the device by the code option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. Once a wake-up event(s) occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy cycle period will be inserted after the wake-up. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal
operation
stops.
* The contents of the on-chip RAM and regis-
ters remain unchanged.
Some registers remain unchanged during reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PD and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 PD 0 u 1 u RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation
* WDT prescaler are cleared. * All I/O ports maintain their original status. * The PD flag is set and the TO flag is cleared.
The system can quit the HALT mode by means of an external reset or an external falling edge signal on port B. An external reset causes a device initialization. Examining the TO and PD flags, the reason for chip reset can be determined. The PD flag is cleared when the system powers up or execute the CLR WDT instruction and is set when the HALT instruction is exe-
Note: u means unchanged.
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Preliminary
RES
HT48RA0A
When a system power up occurs, an SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay.
VDD
Reset circuit
HALT W DT RES LVR OSC1 R eset SST 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tio n W DT T im e - o u t R eset R eset
RES
S S T T im e - o u t C h ip R eset
tS
ST
Reset timing chart The functional unit chip reset status is shown below. PC WDT Prescaler Input/output ports SP Carrier Output 000H Clear Input mode Points to the top of the stack Low level
Reset configuration To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system powers up or when the system awakes from a HALT state.
The chip reset status of the registers is summarized in the following table: Register PC (Program Counter) MP ACC TBLP TBLH STATUS PA PB PC Reset (Power On) 000H -xxx xxxx xxxx xxxx xxxx xxxx --xx xxxx --00 xxxx 1111 1111 1111 1111 ---- ---1 WDT Time-out (Normal Operation) 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --1u uuuu 1111 1111 1111 1111 ---- ---1 RES Reset (Normal Operation) 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu 1111 1111 1111 1111 ---- ---1 RES Reset (HALT) 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --01 uuuu 1111 1111 1111 1111 ---- ---1
Note: u means unchanged x means unknown
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Preliminary
Low voltage reset - LVR The HT48RA0A provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~2.3V, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~2.3V) has to remain in
VDD 3 .6 V V
OPR
HT48RA0A
3 .6 V
V 2 .3 V 2 .2 V
LVR
their original state to exceed 1 ms. If the low voltage state does not exceed 1 ms, the LVR will ignore it and do not perform a reset function. * The LVR uses the OR function with the external RES signal to perform chip reset. * During HALT mode, if the LVR occurs, the device will wake-up and the PD flag will be set as 1, the same as the external RES. Because the operating voltage (V DD ) is 2.3V~3.6V and the LVR operating voltage (VLVR) is 0.9V~2.3V, therefore one margin voltage about 0.1V is needed for proper chip operation. The relationship between VDD and VLVR is shown below.
V 3 .6 V
DD
0 .9 V
Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. Carrier The HT48RA0A provides a carrier output which shares the pin with PC0. It can be selected to be a carrier output (REM) or level output pin (PC0) by code option. If the carrier output option is selected, setting PC0=0 to enable carrier output and setting PC0=1 to disable it at low level output.
V
LVR
L V R D e te c t V o lta g e V L V R = 0 .9 ~ 2 .3 V
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low voltage reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms delay enter the reset mode.
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Preliminary
The clock source of the carrier is implemented by instruction clock (system clock divided by 4) and processed by a frequency divider to yield various carry frequency. Clock Source Carry Frequency= m 2n where m=2 or 3 and n=0~3, both are selected by code option. If m=2, the duty cycle of the carrier output is 1/2 duty. If m=3, the duty cycle of the carrier output can be 1/2 duty or 1/3 duty also determined by code option (with the exception of n=0). Detailed selection of the carrier duty is shown below: m2 2, 4, 8, 16 3 6, 12, 24
n
HT48RA0A
Input/output ports There are an 8-bit bidirectional input/output port, a 6-bit input with 2-bit I/O port and one-bit output port in the HT48RA0A, labeled PA, PB and PC which are mapped to [12H], [14H], [16H] of the RAM, respectively. Each bit of PA can be selected as NMOS output or schmitt trigger with pull-high resistor by software instruction. PB0~PB1 have the same structure with PA, while PB2~PB7 can only be used for input operation (schmitt trigger with pull-high resistors). PC is only one-bit output port shares the pin with carrier output. If the level option is selected, the PC is CMOS output. Both PA and PB for the input operation, these ports are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction MOV A, [m] (m=12H or 14H). For PA, PB0~PB1 and PC output operation, all data are latched and remain unchanged until the output latch is rewritten. When the PA and PB0~PB1 is used for input operation, it should be noted that before reading data from pads, a 1 should be written to the related bits to disable the NMOS device. That is, the instruction SET [m].i (i=0~7 for PA, i=0~1 for PB) is executed first to disable related NMOS device, and then MOV A, [m] to get stable data.
V
Duty Cycle 1/2 1/3 1/2 or 1/3
The following table shows examples of carrier frequency selection. fSYS fCARRIER 37.92kHz 455kHz 56.9kHz Duty 1 only 3 1 only 2 m2 3 2
n
F r e q u e n c y D iv id e r C lo c k S o u r c e ( S y s te m C lo c k /4 ) 3 - b it C o u n te r 1 /2 o r 1 /3 d u ty 1 /2 C o d e O p tio n 1 /3 C a r r ie r D u ty S e le c t
DD
Level
C o d e O p tio n ( c a r r ie r o r le v e l) C a r r ie r R E M /P C 0
C a r r ie r Level
R e a d p a th fo r r e a d - m o d ify - w r ite P C 0 D a ta R e g is te r
Carrier/Level output
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May 17, 2000
Preliminary
After chip reset, PA and PB remain at a high level input line while PC remain at high level output, if the level option is selected. Each bit of PA, PB0~PB1 and PC output latches can be set or cleared by the SET [m].i and CLR [m].i (m=12H, 14H or 16H) instructions respectively. Some instructions first input data and then follow the output operations. For example, SET
HT48RA0A
[m].i, CLR [m], CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. Each line of PB has a wake-up capability to the device by code option. The highest seven bits of PC are not physically implemented, on reading them a 0 is returned and writing results in a no-operation.
V
DD
P u ll- u p R e a d D a ta D a ta b u s S y s te m W a k e -u p C o d e O p tio n PB2~PB7
PB input lines
V
DD
D a ta b u s D W r ite C h ip R e s e t R e a d D a ta S y s te m W a k e -u p
Q CK S Q
W eak P u ll- u p PA0~PA7 PB0~PB1
C o d e O p tio n P B 0 ~ P B 1 o n ly
PA, PB Input/output lines
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May 17, 2000
Preliminary
Code option
HT48RA0A
The following table shows eight kinds of code option in the HT48RA0A. All the code options must be defined to ensure proper system functioning. No. 1 2 Code Option WDT time-out period selection Clock Source where n=8~11. Time-out period= 2n WDT enable/disable selection. This option is to decide whether the WDT timer is enabled or disabled. CLRWDT times selection. This option defines how to clear the WDT by instruction. One time means that the CLR WDT instruction can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, the WDT can be cleared. Wake-up selection. This option defines the wake-up activity function. External input pins (PB only) all have the capability to wake-up the chip from a HALT. Carrier/level output selection. This option defines the activity of PC0 to be carrier output or level output. Carry frequency selection. Clock Source where n=0~3. Carry frequency= (2 or 3) 2n Carrier duty selection. There are two types of selection: 1/2 duty or 1/3 duty. If carrier frequency= Clock Source /(2, 4, 8 or 16), the duty cycle will be 1/2 duty. If carrier frequency= Clock Source /3, the duty cycle will be 1/3 duty. If carrier frequency= Clock Source /(6, 12 or 24), the duty cycle can be 1/2 duty or 1/3 duty. OSC type selection. This option is to decide if an RC or Crystal oscillator is chosen as system clock. If the Crystal oscillator is selected, the XST (Crystal Start-up Timer) default is activated, otherwise the XST is disabled.
3
4 5 6
7
8
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Preliminary
Application Circuits
HT48RA0A
PB1 V
DD
PB2 PB3 PB4 PB5 PB6
PB0 PA3 PA2 PA1 PA0 120W ~240W 300pF X 't a l (s e e N o te ) OSC2 300pF 100kW 0 .1 m F RES
100mF 1W
H T48R A 0A
P C 0 /R E M OSC1
PB7 PA7 PA6 PA5 PA4
Note: It is recommended that a 100mF decoupling capacitor is placed between VSS and VDD. If the crystal has a value above 1MHz the capacitors are not required. The resistance and capacitance for reset circuit should be designed to ensure that the VDD is stable and remains in a valid range of the operating voltage before bringing RES to high.
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Preliminary
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to register with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry with result in data memory Decimal adjust ACC for addition with result in data memory AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Description
HT48RA0A
Instruction Flag Affected Cycle Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m] 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 1 1(1) 1 1(1) Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement
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Preliminary
Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x Table Read TABRDC [m] TABRDL [m] Read EPROM code (current page) to data memory and TBLH Read EPROM code (last page) to data memory and TBLH 2(1) 2(1) Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 Clear bit of data memory Set bit of data memory 1(1) 1(1) Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) Description
HT48RA0A
Instruction Flag Affected Cycle None None C C None None C C None None None None None None None None None None None None None None None None None
None None
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Preliminary
Mnemonic Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog timer Pre-clear Watchdog timer Pre-clear Watchdog timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 Description
HT48RA0A
Instruction Flag Affected Cycle None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD
Note: x: 8 bits immediate data m: 7 bits data memory address A: accumulator i: 0~7 number of bits addr: 11 bits program memory address O: Flag(s) is affected
(1) (2)
-: Flag(s) is not affected : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (4 system clocks). : If a skip to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (4 system clocks). Otherwise the original instruction cycle(s) is unchanged. : and
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the watchdog timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared. Otherwise the TO and PD flags remain unchanged.
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Preliminary
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 3/4 ADCM A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator
HT48RA0A
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
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Preliminary
ADDM A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,x Description Operation Affected flag(s) TC2 3/4 ANDM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add the accumulator to the data memory
HT48RA0A
The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
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Preliminary
CALL addr Description Subroutine call
HT48RA0A
The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to zero. [m] 00H TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
CLR [m].i Description Operation Affected flag(s)
Clear bit of data memory The bit i of the specified data memory is cleared to zero. [m].i 0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
CLR WDT Description Operation Affected flag(s)
Clear watchdog timer The WDT and the WDT Prescaler are cleared (re-counting from zero). The power down bit (PD) and time-out bit (TO) are cleared. WDT and WDT Prescaler 00H PD and TO 0 TC2 3/4 TC1 3/4 TO 0 PD 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
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Preliminary
CLR WDT1 Description Preclear watchdog timer
HT48RA0A
The TD, PD flags, WDT and the WDT Prescaler has cleared (re-counting from zero), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction sets the indicated flag which implies that this instruction has been executed and the TO and PD flags remain unchanged. WDT and WDT Prescaler 00H* PD and TO 0* TC2 3/4 TC1 3/4 TO 0* PD 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
CLR WDT2 Description
Preclear watchdog timer The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting from zero), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction sets the indicated flag which implies that this instruction has been executed and the TO and PD flags remain unchanged. WDT and WDT Prescaler 00H* PD and TO 0* TC2 3/4 TC1 3/4 TO 0* PD 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
CPL [m] Description
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a one are changed to zero and vice-versa. [m] [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
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Preliminary
CPLA [m] Description
HT48RA0A
Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a one are changed to zero and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
DAA [m] Description
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Code Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0) (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by one. [m] [m]-1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
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Preliminary
DECA [m] Description Operation Affected flag(s) TC2 3/4 HALT Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
HT48RA0A
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by one, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PD 1 TO 0 TC2 3/4 TC1 3/4 TO 0 PD 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
INC [m] Description Operation Affected flag(s)
Increment data memory Data in the specified data memory is incremented by one. [m] [m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
INCA [m] Description Operation Affected flag(s)
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by one, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
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Preliminary
JMP addr Description Operation Affected flag(s) TC2 3/4 MOV A,[m] Description Operation Affected flag(s) TC2 3/4 MOV A,x Description Operation Affected flag(s) TC2 3/4 MOV [m],A Description Operation Affected flag(s) TC2 3/4 NOP Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump
HT48RA0A
The contents of the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
No operation No operation is performed. Execution continues with the next instruction. PC PC+1
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Preliminary
OR A,[m] Description Logical OR accumulator with data memory
HT48RA0A
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
OR A,x Description Operation Affected flag(s)
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
ORM A,[m] Description
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
RET Description Operation Affected flag(s)
Return from subroutine The program counter is restored from the stack. This is a two-cycle instruction. PC Stack TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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Preliminary
RET A,x Description Operation Affected flag(s) TC2 3/4 RETI Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return and place immediate data in the accumulator
HT48RA0A
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). PC Stack EMI 1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
RL [m] Description Operation Affected flag(s)
Rotate data memory left The contents of the specified data memory are rotated one bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
RLA [m] Description
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated one bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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Preliminary
RLC [m] Description Rotate data memory left through carry
HT48RA0A
The contents of the specified data memory and the carry flag are rotated one bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RLCA [m] Description
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated one bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation Affected flag(s)
Rotate data memory right The contents of the specified data memory are rotated one bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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Preliminary
RRA [m] Description Rotate right-place result in the accumulator
HT48RA0A
Data in the specified data memory is rotated one bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
RRC [m] Description
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated one bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RRCA [m] Description
Rotate right through carry-place result in the accumulator Data of the specified data memory and the carry flag are rotated one bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
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Preliminary
SBC A,[m] Description Subtract data memory and carry from the accumulator
HT48RA0A
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
Operation Affected flag(s)
SBCM A,[m] Description
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
Operation Affected flag(s)
SDZ [m] Description
Skip if decrement data memory is zero The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if ([m]-1)=0, [m] ([m]-1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if zero The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if ([m]-1)=0, ACC ([m]-1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4
31
Operation Affected flag(s)
OV 3/4
Z 3/4
AC 3/4
C 3/4
May 17, 2000
Preliminary
SET [m] Description Operation Affected flag(s) TC2 3/4 SET [m].i Description Operation Affected flag(s) TC2 3/4 SIZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to one. [m] FFH
HT48RA0A
Set bit of data memory Bit i of the specified data memory is set to one. [m].i 1
Skip if increment data memory is zero The contents of the specified data memory are incremented by one. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if ([m]+1)=0, [m] ([m]+1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if zero The contents of the specified data memory are incremented by one. If the result is zero, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if ([m]+1)=0, ACC ([m]+1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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Preliminary
SNZ [m].i Description Skip if bit i of the data memory is not zero
HT48RA0A
If bit i of the specified data memory is not zero, the next instruction is skipped. If bit i of the data memory is not zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if [m].i0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SUB A,[m] Description Operation Affected flag(s)
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
SUBM A,[m] Description Operation Affected flag(s)
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
SUB A,x Description Operation Affected flag(s)
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
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Preliminary
SWAP [m] Description Operation Affected flag(s) TC2 3/4 SWAPA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Swap nibbles within the data memory
HT48RA0A
The low-order and high-order nibbles of the specified data memory (one of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory-place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SZ [m] Description
Skip if data memory is zero If the contents of the specified data memory are zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if [m]=0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SZA [m] Description
Move data memory to ACC, skip if zero The contents of the specified data memory are copied to the accumulator. If the contents is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if [m]=0, ACC [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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Preliminary
SZ [m].i Description Skip if bit i of the data memory is zero
HT48RA0A
If bit i of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if [m].i=0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
TABRDC [m] Description
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
TABRDL [m] Description Operation Affected flag(s)
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
XOR A,[m] Description Operation Affected flag(s)
Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
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May 17, 2000
Preliminary
XORM A,[m] Description Logical XOR data memory with the accumulator
HT48RA0A
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The zero flag is affected. [m] ACC XOR [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
XOR A,x Description
Logical XOR immediate data to the accumulator Data in the the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The zero flag is affected. ACC ACC XOR x TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
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May 17, 2000
Preliminary
HT48RA0A
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright O 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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May 17, 2000

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